Asia Pacific University Library catalogue


Computer architecture : a quantitative approach / John L. Hennessy, David A. Patterson ; with contributions by Krste Asanović [and 16 others].

By: Hennessy, John LContributor(s): Patterson, David A | Asanovíć, Krste [contributor.]Material type: TextTextPublication details: Cambridge, MA : Morgan Kaufmann Publishers, [2019]Edition: 6th editionDescription: xxix, 617, [284] pages. : illustrations ; 24 cmISBN: 0128119055 (pbk.); 9780128119051 (pbk.)Subject(s): Computer architectureLOC classification: QA76.9.A73 | H46 2019
Contents:
Fundamentals of quantitative design and analysis -- Memory hierarchy design -- Instruction-level parallelism and its exploitation -- Data-level parallelism in vector, SIMD, and GPU architectures -- Thread-level parallelism -- Warehouse-scale computers to exploit request-level and data-level parallelism -- Domain-specific architectures -- Instruction set principles -- Review of memory hierarchy -- Pipelining: basic and intermediate concepts -- Online appendices. Storage systems -- Embedded systems -- Interconnection networks -- Vector processors in more depth -- Hardware and software for VLIW and EPIC -- Large-scale multiprocessors and scientific applications -- Computer arithmetic -- Survey of instruction set architectures -- Advanced Concepts on Address Translation -- Historical perspectives and references.
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QA76.9.A73 H46 2007 c.2 Computer architecture : QA76.9.A73 H46 2012 c.1 Computer architecture : QA76.9.A73 H46 2012 c.2 Computer architecture : QA76.9.A73 H46 2019 c.1 Computer architecture : QA76.9.A73 H46 2019 c.2 Computer architecture : QA76.9.A73 H83 1993 c.1 Advanced computer architecture : QA76.9.A73 K34 1996 c.1 Computer architecture :

Includes bibliographical references (pages R1-R36) and index.

Fundamentals of quantitative design and analysis -- Memory hierarchy design -- Instruction-level parallelism and its exploitation -- Data-level parallelism in vector, SIMD, and GPU architectures -- Thread-level parallelism -- Warehouse-scale computers to exploit request-level and data-level parallelism -- Domain-specific architectures -- Instruction set principles -- Review of memory hierarchy -- Pipelining: basic and intermediate concepts -- Online appendices. Storage systems -- Embedded systems -- Interconnection networks -- Vector processors in more depth -- Hardware and software for VLIW and EPIC -- Large-scale multiprocessors and scientific applications -- Computer arithmetic -- Survey of instruction set architectures -- Advanced Concepts on Address Translation -- Historical perspectives and references.

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