Introduction to logic synthesis using Verilog HDL / Robert B. Reese, Mitchell A. Thornton.
Material type:
Item type | Current library | Collection | Call number | Copy number | Status | Date due | Barcode |
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APU Library Open Shelf | Book | TK7868.L6 R44 2006 c.1 (Browse shelf (Opens below)) | 1 | Available (No use restrictions) | 00024498 |
Includes bibliographical references.
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